An analogue to digital converter of the counter type having characteristics high in accuracy has been frequenctly employed in audio systems such as a PCM audio system. Shown in FIG. 1 is a typical example of such a counter type analogue to digital converter. In FIG. 1, reference numeral 1 designates an integrator which is composed of an operational amplifier 1A and a capacitor 1B. An input terminal 3 is coupled through a sampling switch 2 to the input terminal of the integrator 1 together with a constant current source section 4. The sampling switch 2 is subjected to an ON-OFF control operation in response to a predetermined sampling pulse P.sub.s thereby to switch an input analogue signal applied to the input terminal 3. The integrator 1 is operative to carry out an integrating operation for the input analogue signal applied through the sampling switch 2. Further, both a constant current I.sub.0 from a first constant current source 4A and a constant current I.sub.1 from a second constant current source 4B are supplied to the integrator 1 through current switches 4C and 4D, respectively, to be integrated therein. The constant current sources 4A and 4B and the current switches 4C and 4D constitute the constant current source section 4. The constant currents I.sub.0 and I.sub.1 are determined to satisfy the relation of (I.sub.0 +I.sub.1)/I.sub.1 =2.sup.7 and I.sub.0 =127.multidot.I.sub.1. The output terminal of the integrator 1 is coupled to the input terminal of a comparing section 5.
The comparing section 5 is composed of a first comparator 5A, a second comparator 5B and a reference voltage source 5C. The output voltage of the integrator 1 is supplied to both comparison input terminals of the first and second comparator 5A and 5B, respectively. The reference voltage of the reference voltage source 5C is supplied to a reference input terminal of the first comparator 5A whereas a reference input terminal of the second comparator 5B is grounded. The output terminals of the first and second comparators 5A and 5B are connected to both a control section 6 and a counter section 7.
The control section 6 is operative to produce the above-described sampling pulse P.sub.s to be supplied to a control terminal of the sampling switch 2. Further, the control section 6 is operative to produce a control signal P.sub.1 to be supplied to control terminals of the first and second comparator 5A and 5B and to produce control signals P.sub.2 and P.sub.3 to be supplied to control terminals of the current switches 4C and 4D, respectively. A comparison output C.sub.1 of the first comparator 5A and a comparison output C.sub.2 of the second comparator 5B are supplied to the control section 6.
The counter section 7 includes a first counter 7A for higher bits and a second counter 7B for lower bits. A control signal C.sub.0 is supplied from the control section 6 to a start terminal of the first counter 7A and the comparison output C.sub.1 of the first comparator 5A is supplied to a stop terminal of the first counter 7A and a start terminal of the second counter 7B. Further, the comparison output C.sub.2 is supplied to a stop terminal of the second counter 7B.
The operation of the analogue to digital converter described above will be explained hereinafter with reference to the accompanying FIG. 2.
Now, when the input analogue signal is applied to the input terminal 3, during a period of time t.sub.0 to t.sub.1 shown in FIGS. 2A to 2H, the sampling pulse P.sub.s takes a high level as shown in FIG. 2A and this results in that the sampling switch 2 is turned on. Accordingly, the integration is carried out in accordance with the input analogue signal in the integrator 1, so that an output voltage V.sub.0 of the integrator 1 decreases as shown in FIG. 2B. This output voltage V.sub.0 corresponds to the level of the input analog signal supplied to the input terminal 3 during the period of the time t.sub.0 to t.sub.1. When the sampling pulse P.sub.s falls down to a lower level at the time t.sub.1, the sampling switch 2 is thus turned off. At this time, the control signal P.sub.1 from the control section 6 rises up to a high level as shown in FIG. 2C so that both first and second comparators 5A and 5B in the comparing section 5 are turned into the active state. Simultaneously, the first counter 7A is supplied with the control signal C.sub.O as shown in FIG. 2F from the control section 6 thereby to commence the counting operation thereof. Further, upon falling down of the sampling pulse P.sub.s, the control signals P.sub.2 and P.sub.3 both having a high level as shown in FIGS. 2D and 2E are supplied from the control section 6 to the current switches 4C and 4D so as to render the current switches 4C and 4D conductive. Consequently, the sum of the constant currents I.sub.0 and I.sub.1 is allowed to flow into the integrator 1 through the switches 4C and 4D and the integrator 1 carries out the integration in accordance therewith. This results in that the output voltage V.sub.0 of the integrator 1 increases linearly. The output voltage V.sub.0 is compared with the reference voltage V.sub.1 supplied from the reference voltage source 5C in the first comparator 5A. Then, at the time t.sub.2 when the output voltage V.sub.0 exceeds the reference voltage V.sub.1, the first comparator 5A operates to produce the comparison output C.sub.1 as shown in FIG. 2G and the first counter 7A is stopped in response to the rising edge of the comparison output C.sub.1 whereas the second counter 7B is caused to commence the counting operation thereof. Accordingly, the first counter 7A carries out the counting operation during the period of the time t.sub.1 to t.sub.2. Since the control signal P.sub.2 falls to a low level when the output voltage V.sub.0 is equal to the reference voltage V.sub.1, the current switch 4A is turned off at the time t.sub.2, and as a result of this, the constant current I.sub.1 is only supplied from the second constant current source 4B to the integrator 1. Then, the integration is carried out in accordance with the constant current I.sub.1 in the integrator 1, and the output voltage V.sub.0 increases linearly again during the period of the time t.sub.2 to t.sub.3 and is compared with the reference voltage V.sub.2 (0V in this embodiment) in the second comparator 5B. At the time t.sub.3 when the output voltage V.sub.0 becomes equal to the reference voltage V.sub.2, the second comparator 5B generates the comparison output C.sub.2 as shown in FIG. 2H. When the comparison output C.sub.2 rises up to a high level, the second counter 7B is stopped. Accordingly, the second counter 7B carries out the counting operation during the period of the time t.sub.2 to t.sub.3. Thereafter, when the comparison output C.sub.2 falls down to a low level and the rising edge of the subsequent sampling pulse P.sub.s appears at time t.sub.4, the above-described operation is performed repeatedly.
The count result of the counter 7A at the time t.sub.2 and the count result of the counter 7B at the time t.sub.3 are latched and loaded to a shift register. Then, the results are derived in a serial mode, so that digital data consisting of higher bits and lower bits, which represent the integration output of the constant current (I.sub.0 +I.sub.1) and the integration output in response to the constant current I.sub.1, respectively, can be obtained.
In case that, with such a conventional counter type analogue to digital converter described above, analogue to digital conversions with respect to a plurality of input analogue signals, for instance, a left-channel audio signal and a right channel audio signal contained in a stereophonic audio signal, are achieved, an analogue to digital converter as shown in FIG. 3, in which a pair of circuit blocks containing the integrator 1 to the counter section 7 as shown in FIG. 1 and an integrator 1' to a counter section 7' similar to those shown in FIG. 1, respectively, are provided and the left and right channel signals are applied to input terminals of the circuit blocks, respectively, has been employed. In the device of FIG. 3, a parallel/serial converter 8 such as a shift register is further provided to the output ends of the respective counter sections 7 and 7', so that digital data obtained by subjecting the right channel audio signal to the analogue to digital conversion and that obtained by processing the left channel audio signal similarly are produced alternately as serial data.
However, such a conventional device is required to have a couple of analogue to digital conversion circuit arrangements which are identical in circuit construction, and this results in the disadvantages that the device is intricate in circuit construction and the manufacturing cost thereof is increased.
In order to eliminate the drawbacks accompanying the above-described conventional device, an analogue to digital converter of a different type in which a single analogue to digital conversion circuit arrangement is provided and, as shown in FIG. 4, an input end of an integrator 1 therein is connected to both input terminal 11 and 11' through two sampling switches 10 and 10' which are turned on alternately by a control section 9, has been proposed. In such a device, the input terminals 11 and 11' are supplied with respectively left and right channel audio signals which are subjected alternately to an analogue to digital conversion through integrating operation and counting operation so as to produce digital data representing the both audio signals.
In this conventional device, excepting the sampling switches, the single analogue to digital conversion circuit arrangement is only required and therefore the circuit construction is made simple. However, since the single analogue to digital conversion circuit arrangement is used in common with respect to two input analogue signals alternately to produce outputs converted to digital signals, there is disadvantage that a relatively long time is required to achieve analogue to digital conversion for the two input analogue signals.